Skip to main content
English
中文
Log In
Log in
Log in with ORCID
NTU Single Sign On
New user? Click here to register.
Have you forgotten your password?
Home
College of Electrical Engineering and Computer Science / 電機資訊學院
Electrical Engineering / 電機工程學系
Gate-Level Dual-Threshold Static Power Optimization Methodology (GDSPOM) Using Path-Based Static Timing Analysis (STA) Technique
Details
Gate-Level Dual-Threshold Static Power Optimization Methodology (GDSPOM) Using Path-Based Static Timing Analysis (STA) Technique
Journal
PATMOS
Pages
237-246
Date Issued
2006-09
Author(s)
B. Chung
J. B. Kuo
JAMES-B KUO
URI
http://scholars.lib.ntu.edu.tw/handle/123456789/325388
Type
conference paper