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  4. Leakage-aware task scheduling for partially dynamically reconfigurable FPGAs
 
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Leakage-aware task scheduling for partially dynamically reconfigurable FPGAs

Journal
ACM Transactions on Design Automation of Electronic Systems
Journal Volume
14
Journal Issue
4
Date Issued
2009
Author(s)
CHIA-LIN YANG  
Yuh, P.-H.
Yang, C.-L.
Li, C.-F.
Lin, C.-H.
CHIA-LIN YANG  
DOI
10.1145/1562514.1562520
URI
http://www.scopus.com/inward/record.url?eid=2-s2.0-70349121655&partnerID=MN8TOARS
http://scholars.lib.ntu.edu.tw/handle/123456789/349154
Abstract
As technology continues to shrink, reducing leakage power of Field-Programmable Gate Arrays (FPGAs) becomes a critical issue for the practical use of FPGAs. In this article, we address the leakage issue of partially dynamically reconfigurable FPGA architectures with sleep transistors embedded into FPGA fabrics. In particular, we focus on eliminating leakage waste due to the delay between reconfiguration and execution time of a task. For partially dynamically reconfigurable FPGAs, the configuration prefetching technique is commonly used to hide runtime reconfiguration overhead. With prefetching, the configuration of a task is loaded into FPGAs as early as possible. Therefore, there is often a delay between reconfiguration and execution time of a task. In this period of time, the SRAM cells allocated to a task cannot be turned off even though they are not utilized. In this article, we propose a two-stage task scheduling methodology to reduce leakage waste due to the delay between reconfiguration and execution time of a task without sacrificing performance. In the first stage, a performance-driven task scheduler that targets at minimizing the schedule length is invoked to generate an initial placement. In the second stage, a postplacement leakage-aware task scheduling is applied to refine the initial placement such that leakage waste is minimized provided that the schedule length is not increased. To solve the postplacement leakage optimization problem, we propose two algorithms. The first one is an optimal algorithm based on Integer Linear Programming (ILP). The second algorithm is a heuristic approach that iteratively refines the placement to reduce leakage waste. Experimental results on real and synthetic designs show that the efficiency and effectiveness of the proposed postplacement leakage reduction techniques.
Type
journal article

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