A BiCMOS dynamic full adder circuit for VLSI implementation of high-speed parallel multipliers using Wallace tree reduction architecture
Resource
Bipolar/BiCMOS Circuits and Technology Meeting, 1992., Proceedings of the 1992
Journal
Bipolar/BiCMOS Circuits and Technology Meeting, 1992.
Pages
-
Date Issued
1992-10
Date
1992-10
Author(s)
DOI
N/A
Abstract
This paper presents a BiCMOS dynamic full adder circuit for VLSI implementation of high-speed parallel multipliers using Wallace tree reduction architecture. With the BiCMOS dynamic full adder circuit, an 8x8 multiplier designed based on a 2(im BiCMOS technology shows a 6x improvement in speed as compared to the CMOS static one. © 1992 IEEE.
Subjects
Adders; BiCMOS technology; Electron multipliers; Forestry; Frequency multiplying circuits; Memory architecture; Timing circuits; VLSI circuits; Bi-CMOS; Dynamic full adders; High Speed; Parallel multipliers; VLSI implementation; Wallace tree; Parallel architectures
SDGs
Type
journal article
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