High SCR design for one-transistor split-gate full-featured EEPROM
Resource
IEEE Electron Device Letters 25 (7): 498-500
Journal
IEEE Electron Device Letters
Journal Volume
EDL-25
Journal Issue
7
Pages
498-500
Date Issued
2004-07
Author(s)
Chu, Wen-Ting
Lin, Hao-Hsiung
Wang, Yu-Hsiung
Hsieh, Chia-Ta
Sung, Hung-Cheng
Lin, Yung-Tao
Wang, C.S.
Abstract
A high source-coupling ratio design for full-featured EEPROM composed of one-transistor split-gate cells with a cell area of less than 22 F/sup 2/ is proposed. This is in contrast to a traditional cell that requires an extra select transistor and is not area economic when compared to the new design cell. In this design, the cell adopts poly-poly Fowler-Nordheim tunneling to erase, and an inhibited source voltage is used for the unselected cell to achieve bit erase. It has demonstrated excellent program and erase disturb margins and passed 300 k program/erase (P/E) cycling test. It was found that after P/E cycling stress, the cell gains a better erase disturb immunity.
Type
journal article
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