Design and Implementation of CMOS Wireless Receiver Circuits for 24-GHz Communication Systems
Date Issued
2007
Date
2007
Author(s)
Chen, Yu-Hsin
DOI
en-US
Abstract
As the demands for wider bandwidth in wireless communication continue to expand, the development of low-cost and high-performance monolithic microwave integrated circuits (MMICs) have attracted great attention. Conventionally, the high-frequency integrated circuits were realized by III-V compound semiconductor and SiGe BiCMOS process due to their superior device performance. Owing to unparalleled advantages in both fabrication cost and denser integration, the CMOS technology appears to be well suited to implement these designs. However, it still remains a challenge for such RF building blocks to be integrated in a standard CMOS process due to its significant substrate losses and inferior high-frequency properties of the active devices. Consequently, this thesis describes the design consideration of the CMOS process for the individual building blocks then presents several novel circuit techniques to reach the requirements for the system designs.
First, a transmit/receive (T/R) switch for the 24-GHz ISM band application implemented in a standard 0.18-m CMOS process is demonstrated. A technique to enhance the isolation performance is proposed for the T/R switch. Reasonable isolation and insertion loss are achieved with an additional switch. Besides, impedance transformation networks (ITNs) is utilized to reduce the source and load impedance seen from the switch to increase the power handling capability. The fabricated SPDT (single-pole double-throw) switch at 24-GHz exhibits an insertion loss of 2.5 dB and an isolation of 20 dB while maintaining an input and output return loss better than 14 dB and 19 dB, respectively. Owing to the use of the ITNs, the measured Pin-1dB of the switch is 24.2 dBm.
Secondly, a receiver architecture is presented for operations at the 24-GHz frequency band. By monolithically integrating the LNA, the down-conversion mixer and the IF amplifiers, the receiver frontend is realized in a 0.18-m CMOS process, exhibiting enhanced circuit performance in terms of conversion gain and noise figure. With an IF frequency of 4.82-GHz, the fabricated circuit demonstrates a conversion gain of 28.4 dB and a noise figure of 6.0 dB while maintaining an input return loss better than 14 dB. The measured Pin-1dB and IIP3 of the receiver frontend are -23.2 and -13.0 dBm, respectively. The power consumption for the receiver frontend is 54mW at a supply voltage of 1.8 V,.
Finally, a signal generator which provides the required LO outputs for the proposed receiver architecture is presented. The proposed LO generator consists of a 19-GHz low-phase-noise voltage-controlled oscillator (VCO), a 4:1 frequency divider and a quadrature phase tuning circuit. With a noise filtering technique and gm-boosting capacitive feedback, the VCO exhibits low phase noise with adequate frequency tuning range. Besides, an interpolation technique, which is originally developed for ring oscillators, is adopted for the phase tuning the quadrature signal provided by the frequency divider to obtain accurate phases.
Subjects
24-GHz
微波單晶積體電路
接收機前端電路
發送/接收切換器
低相位雜訊壓控振盪器
MMIC
receiver frontend
T/R siwtch
low phase noise VCO
Type
thesis
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