A 10-GHz CMOS Frequency Synthesizer with an Agile VCO Calibration
Date Issued
2005
Date
2005
Author(s)
Lai, Yu-Jen
DOI
en-US
Abstract
Owing to the popularity of various networking and communication applications, the demands on wide bandwidth and high data rate grow stronger. Many wireless/wireline communication systems are therefore moving towards higher operating frequencies. To meet this trend, this research has developed a 10-GHz frequency synthesizer, which can be applied to a 10-G Ethernet, wireless, or fiber optic applications. In order to achieve low-cost design goal, CMOS technology has been selected to implement this design. Furthermore, novel system and circuit architectures are also proposed to attain high performance.
For a conventional phase-locked loop (PLL) type frequency synthesizer, the voltage-controlled oscillator (VCO) gain (KVCO, MHz/V) must be designed to be large enough in order to cover a wide frequency tuning range. This, however, degrades the phase noise and spurs performance. This issue can be alleviated by breaking a continuous wide-range tuning curve into several narrower curves with sufficient frequency overlap. It is typically achieved by employing a switched capacitor array in the LC-VCO to implement such discrete tuning. This method requires a VCO calibration circuit to search for the proper curve. In general, the VCO calibration can be categorized into closed- and opened-loop approaches. Both have advantages and disadvantages. However, one common issue is that they both require considerable amount of time to complete the calibration task, therefore wasting precious communication time. This work first addresses this issue and proposes a novel agile VCO calibration architecture.
During the calibration, the PLL loop is opened. Once the calibration is completed, the PLL loop will then close and lock to the desired channel frequency. The major difference between this approach proposed here and the conventional one is that this method performs the calibration by comparing the length of periods of FREF and FVCO/N, rather than counting cycles.
For the circuit implementation, there two signals (FREF and FVCO/N) are first divided by two in frequency, such that the output pulse widths represent their signal periods. During comparison, the phase difference of the rising edges of these two signals (now FREF/2 and FVCO/2N) discharges a capacitor; while the phase difference of the falling edges of FREF/2 and FVCO/2N charges the same capacitor. The net voltage change across the capacitor is a representative of the period difference between these two signals, and is based upon to select the propose VCO tuning curve (VCO calibration). In order to enhance the accuracy of the proposed architecture, various mixed-mode circuits, such as Phase Selector, are also proposed and developed. Due to the nature of this calibration approach (comparing signal periods rather than counting signal cycles), the calibration can be completed in just a few cycles, therefore it is much faster than the conventional ones (both closed- and opened-loop methods). From the communication point of view, this allows more time spending on the data transmission/reception, increasing actual data throughput.
Another circuit innovation of this work is in the VCO biasing technique. Conventional current source tends to contribute phase noise to the VCO output significantly. Here, the VCO is biased with a programmable switched transistor array to alleviate this issue. From the simulation, this approach also requires less area for a given performance.
This 10-GHz CMOS frequency synthesizer has been fabricated in TSMC 0.18 micro-meter technology. This chip has been measured. All circuit components, including the VCO, PLL, Loop Filter, and the calibration circuit have been integrated into the single chip.
Subjects
選頻
鎖相迴路
頻率合成器
calibration
PLL
frequency synthesizer
Type
thesis
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