High resolution digital timing vernier circuit for Automatic-Test-Equipment (ATE)
Date Issued
2006
Date
2006
Author(s)
Wang, Ting-Yuan
DOI
zh-TW
Abstract
Owing to the progress of the semiconductor process and quickly development of the communicational consumer electronics, the circuit design of high-speed digital SoC becomes essential and more complexity. Meanwhile, the advanced digital data transmission protocol requires the high precision signal. Thus, designing timing vernier with fine resolution to generate the high precision signal in the automatic-testing-equipment (ATE) is the key issue for furtur testing.
A timing vernier must be designed with high precision, fine resolution, wide programmable range, less complexities and low costs. At the first, we propose a novel design of fast and long constant-time up/down counter using ladder architecture as the coarse delay timing vernier in charpater II. The counter is designed to generate constant carry propagation with any count size. Carry backward[1] and count down prediction mechanism [2]with ladder architecture are adapted to achieve this design. The main problem behind the up/down counter is to recognize that the extra difficulty with an up/down counter (vs. up-only or down-only) when the counter changes direction from counting up to counting down. For dealing with this difficulty, the Linear Feedback Shift Register (LFSR) counting cells[3] and carry selection mechanism is used. When the proposed counter is working as a general counter when counting up or down only. Once the direction changed, the prediction carry signal, carry or borrow, and the data propagation direction is switched in LFSR.
A 18-bit 525MHz carry backward synchronous up/down counter using LFSR counting cells with ladder architecture is presented. This architecture has been fully simulated with TSMC 0.35μm CMOS process. The die size is 0.65mm × 0.5mm
The charpter III of this thesis presents a multiple channel programmable timing vernier with single cyclic delay line using pulse width self controlled delay cells (PWSCDC). The features of highly integrating several timing vernier using single delay line reduces the complexity and cost in ATE. The timing verniers in each channel are propagated from one delay chain. Thus, this structure eliminates the offset of timing verniers between channels which are caused by the circuit mismatches and process variations. This thesis presents the design and measurement results of multiple channel programmable timing verniers using single cyclic delay line for high-speed automatic test equipment (ATE) with 37.5ps resolution and 1ms programmable delay range. There are three timing generators and each one consists of a 19bit 360MHz count-up counter, a 19bit cycle comparator, a zero cycle detector, a control word splitter, and an output selector with an 8x-interpolator. A 32-stage cyclic delay line is constructed by pulse-width self-controlled delay cell (PWSCDC). The proposed timing generator uses the TSMC 0.35 μm 1P4M process with a die size of 2.33 mm x 2.17 mm. The dynamic non-linearity (DNL) is less than ±0.6 LSB (37.5ps). The integral non-linearity (INL) is between –1 LSB and 7 LSB before calibration, and is between±0.4 LSB after root-mean-square value calibration. The multi-channel phase mismatch (MCPM) is 19ps (RMS) and jitter is 13.7ps (RMS).
After achieving the design features of wide programmable delay range and reducing complexities of timeing vernier, we presents a novel timing vernier with ultra-fine resolution using N-dimensional DLL arrays in charpter IV. The proposed architecture is verified with N = 3 using TSMC 0.18um 1P6M process. Fewer delay cells are used to design DLL arrays than other timing vernier circuits. Owing to the N-dimensional structure, the resolution can be designed as multiple result of the number of delay cells in each delay line easily.
The proposed DLL arrays use 133 MHz clock as the reference clock. A reference voltage switching mechanism (RVSM) is used to switch each delay cell between two different reference voltages in the programmable delay line (PDL). Thus, the propagation of each delay cell can be switched in the same delay cell. Proposed timing vernier generates the delay signal with the resolution of 15ps and the operation frequency of PDL is designed from 50 MHz to 500 MHz. The delay range of the timing vernier can be programmed from 0ps to 1560ps. The measurement result of DNL is less than ± 0.5LSB (7.5ps)
In most timing vernier circuits, analog charge pump and current starved delay cells are generally used in the delay locked loop for generating reference timing vernier. In charpter V, we proposed a timing vernier with all digital delay locked loop for simplifying the design with process migration, eliminating the sensitivities with process variation and reducing peak-to-peak jitters. Meanwhile, the locked-detecting mechanism is also presented with jitter analysis. An all digital delay locked loop with 6ps resolutions uses the TSMC 0.35 μm 1P4M process with post simulation verified. The delay range is from 0ps to 1.72ns.
This thesis has proposed several timing vernier architectures to achieve the advanced features for desing timing vernier. In charpter VI of this thesis, a wide range and high-speed time-to-digital converter (TDC) based on a single cyclic delay line is proposed for timing vernier calibration. The TDC is designed to measure the vernier timing and calibrating the generated vernier for higher precision in each timing vernier circuit.
The time-to-digital converter can operate in both single-shot and continuously triggered mode with zero re-arm time, which can be synchronized with a maximum operation frequency of 125MHz. The measurement range of pulse under test (PUT) is from 320ps to 10ms using a 20-bit counter. The resolution can reach 163ps. The DNL is less than ±0.13LS, and the INL is less than ±0.05 LSB after calibration. The TDC has been implemented in 0.35µm 1P4M process with chip area 1.48mm × 1.41mm.
A timing vernier must be designed with high precision, fine resolution, wide programmable range, less complexities and low costs. At the first, we propose a novel design of fast and long constant-time up/down counter using ladder architecture as the coarse delay timing vernier in charpater II. The counter is designed to generate constant carry propagation with any count size. Carry backward[1] and count down prediction mechanism [2]with ladder architecture are adapted to achieve this design. The main problem behind the up/down counter is to recognize that the extra difficulty with an up/down counter (vs. up-only or down-only) when the counter changes direction from counting up to counting down. For dealing with this difficulty, the Linear Feedback Shift Register (LFSR) counting cells[3] and carry selection mechanism is used. When the proposed counter is working as a general counter when counting up or down only. Once the direction changed, the prediction carry signal, carry or borrow, and the data propagation direction is switched in LFSR.
A 18-bit 525MHz carry backward synchronous up/down counter using LFSR counting cells with ladder architecture is presented. This architecture has been fully simulated with TSMC 0.35μm CMOS process. The die size is 0.65mm × 0.5mm
The charpter III of this thesis presents a multiple channel programmable timing vernier with single cyclic delay line using pulse width self controlled delay cells (PWSCDC). The features of highly integrating several timing vernier using single delay line reduces the complexity and cost in ATE. The timing verniers in each channel are propagated from one delay chain. Thus, this structure eliminates the offset of timing verniers between channels which are caused by the circuit mismatches and process variations. This thesis presents the design and measurement results of multiple channel programmable timing verniers using single cyclic delay line for high-speed automatic test equipment (ATE) with 37.5ps resolution and 1ms programmable delay range. There are three timing generators and each one consists of a 19bit 360MHz count-up counter, a 19bit cycle comparator, a zero cycle detector, a control word splitter, and an output selector with an 8x-interpolator. A 32-stage cyclic delay line is constructed by pulse-width self-controlled delay cell (PWSCDC). The proposed timing generator uses the TSMC 0.35 μm 1P4M process with a die size of 2.33 mm x 2.17 mm. The dynamic non-linearity (DNL) is less than ±0.6 LSB (37.5ps). The integral non-linearity (INL) is between –1 LSB and 7 LSB before calibration, and is between±0.4 LSB after root-mean-square value calibration. The multi-channel phase mismatch (MCPM) is 19ps (RMS) and jitter is 13.7ps (RMS).
After achieving the design features of wide programmable delay range and reducing complexities of timeing vernier, we presents a novel timing vernier with ultra-fine resolution using N-dimensional DLL arrays in charpter IV. The proposed architecture is verified with N = 3 using TSMC 0.18um 1P6M process. Fewer delay cells are used to design DLL arrays than other timing vernier circuits. Owing to the N-dimensional structure, the resolution can be designed as multiple result of the number of delay cells in each delay line easily.
The proposed DLL arrays use 133 MHz clock as the reference clock. A reference voltage switching mechanism (RVSM) is used to switch each delay cell between two different reference voltages in the programmable delay line (PDL). Thus, the propagation of each delay cell can be switched in the same delay cell. Proposed timing vernier generates the delay signal with the resolution of 15ps and the operation frequency of PDL is designed from 50 MHz to 500 MHz. The delay range of the timing vernier can be programmed from 0ps to 1560ps. The measurement result of DNL is less than ± 0.5LSB (7.5ps)
In most timing vernier circuits, analog charge pump and current starved delay cells are generally used in the delay locked loop for generating reference timing vernier. In charpter V, we proposed a timing vernier with all digital delay locked loop for simplifying the design with process migration, eliminating the sensitivities with process variation and reducing peak-to-peak jitters. Meanwhile, the locked-detecting mechanism is also presented with jitter analysis. An all digital delay locked loop with 6ps resolutions uses the TSMC 0.35 μm 1P4M process with post simulation verified. The delay range is from 0ps to 1.72ns.
This thesis has proposed several timing vernier architectures to achieve the advanced features for desing timing vernier. In charpter VI of this thesis, a wide range and high-speed time-to-digital converter (TDC) based on a single cyclic delay line is proposed for timing vernier calibration. The TDC is designed to measure the vernier timing and calibrating the generated vernier for higher precision in each timing vernier circuit.
The time-to-digital converter can operate in both single-shot and continuously triggered mode with zero re-arm time, which can be synchronized with a maximum operation frequency of 125MHz. The measurement range of pulse under test (PUT) is from 320ps to 10ms using a 20-bit counter. The resolution can reach 163ps. The DNL is less than ±0.13LS, and the INL is less than ±0.05 LSB after calibration. The TDC has been implemented in 0.35µm 1P4M process with chip area 1.48mm × 1.41mm.
Subjects
時序游標產生器
迴圈式延遲線
延遲鎖定迴路陣列
時序數位轉換器
數位延遲鎖定迴路
Time-to-Digital Converter
TDC
Timing Vernier
DLL arrays
Digital Delay Locked Loop
DDLL
Type
thesis
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