A closed-form back-gate-bias related inverse narrow-channel effect model for deep-submicron VLSI CMOS devices using shallow trench isolation
Journal
IEEE Transactions on Electron Devices
Journal Volume
47
Journal Issue
4
Pages
725-733
Date Issued
2000
Author(s)
Abstract
This paper reports an analytical inverse narrow-channel effect threshold voltage model for shallow-trench-isolated (STI) CMOS devices using a conformai mapping technique to simplify the two-dimensional (2-D) analysis. As verified by the experimentally measured data and the 2-D simulation results, the analytical model predicts well the inverse narrow-channel effect threshold voltage behavior of the STI CMOS devices. Based on the study, the inverse narrow-channel effect also affects the saturation-region output conductance of a small-geometry STI CMOS device in addition to the short-channel effect. © 2000 IEEE.
Subjects
Conformai mapping technique; Inverse narrow-channel effect; Small geometry; STI
SDGs
Other Subjects
Computational geometry; Computer simulation; Conformal mapping; Gates (transistor); Semiconductor device models; Threshold voltage; VLSI circuits; Deep submicron devices; Inverse narrow channel effect; Shallow trench isolation (STI); CMOS integrated circuits
Type
journal article