Study of Source and Body Contacts Layout Design to High Voltage NMOS ESD Protection Devices
Date Issued
2009
Date
2009
Author(s)
Wu, Ho-Chun
Abstract
This study analyzes the characteristic of ESD (electro-static-discharge) of high voltage NMOS (N-type metal oxide semiconductor) transistor current and voltage when NMOS is turned-on in high voltage. When the width of bypass MOS in the ESD protection circuit has to layout in the multi-finger type so as to decrease the layout area cost, in the mean while, due to the snapback breakdown of NMOS and the resistance connecting the base of the parasitic lateral bipolar transistor in the substrate is individually different. These sub-multi-finger NMOS’can not be turned on simultaneously. The ESD current is passed in few MOS’. The uniform turn-on of NMOS results in the endurance of ESD can increase as the width of protection device is increased. In this condition, it is more difficult to design an ESD protection circuit.his thesis is trying to change the layout parameters of source and bulk of a multi-finger NMOS so as to find out optimal layout rules of a high voltage ESD protection device. Different layout parameter of NMOS’are tested. The uniformity of ESD devices are measured by transmission pulse generator. The results of this study can provide evidences for further study of high voltage ESD device.
Subjects
High Voltage NMOS ESD
Source Contacts
Body Contacts
Layout Design
Type
thesis
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