Novel crosstalk modeling for multiple through-silicon-vias (TSV) on 3-D IC: Experimental validation and application to Faraday cage design
Journal
2012 IEEE 21st Conference on Electrical Performance of Electronic Packaging and Systems, EPEPS 2012
Pages
232-235
Date Issued
2012
Author(s)
Chang, Y.-J.
Chuang, H.-H.
Lu, Y.-C.
Chiou, Y.-P.
Wu, T.-L.
Chen, P.-S.
Wu, S.-H.
Kuo, T.-Y.
Zhan, C.-J.
Lo, W.-C.
Abstract
An equivalent circuit model to characterize the crosstalk strength in multiple TSVs is newly proposed. In this model, all the values of lumped elements in the model are given in closed-form formulas. Therefore, the computation effort for constructing the model of multiple TSVs is much lower than other previous works. The accuracy is verified by the measurement for a nine stacked silicon chips and the full-wave simulation results. The proposed model is then utilized to the design for crosstalk mitigation. With the advantages of smaller occupied area (lower cost), a rhombus-grounded Faraday cage design is recommended with lower cost and similar performance compared to conventional Faraday cage concept.
Type
conference paper