A Pyramid-Free, Memory-Efficient RGB-D Visual Odometry Accelerator via Algorithm–Hardware Codesign
Journal
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Journal Volume
34
Journal Issue
5
Start Page
1604
End Page
1616
ISSN
1063-8210
1557-9999
Date Issued
2026-03-13
Author(s)
Abstract
Recent advancements in spatial computing have transformed the interaction paradigm between digital information and physical environments, enabling context-aware applications that enhance daily activities across healthcare, education, entertainment, and industry. At the heart of spatial computing lies visual odometry (VO), which estimates real-time device motion to accurately align virtual content with the real world. However, achieving real-time RGB-D VO on mobile and wearable platforms remains challenging due to limited computing resources, particularly stringent memory constraints. In this article, we present a memory-efficient RGB-D VO accelerator developed via algorithm-hardware codesign. Our method significantly reduces memory consumption by employing a hybrid pipeline that integrates sparse, feature-based initialization with dense, direct-based optimization, thereby eliminating memory-intensive image pyramids. To the best of our knowledge, this is the first pyramid-free RGB-D VO accelerator that achieves real-time operation with only 128 kB of on-chip SRAM, demonstrating the effectiveness of algorithm-hardware codesign in memory-constrained environments. Implemented in TSMC 40-nm CMOS technology, the proposed architecture achieves a 32.78% reduction in memory usage, a 10.20% smaller chip area, and a 1.68× improvement in frame rate compared to baseline designs, efficiently processing RGB-D data at 34.4 f/s using only 128 kB of on-chip memory.
Subjects
Accelerator
augmented reality
computer vision
hardware-algorithm codesign
visual odometry (VO)
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Type
journal article