Area, Delay, Power, and Noise Optimization for Transmission Lines
Date Issued
2004-07-31
Date
2004-07-31
Author(s)
DOI
922215E002016
Abstract
As the operation frequency reaches gigahertz in
very deepsubmicron designs, the effect of on-chip
inductance on circuit performance can no longer be
neglected. Therefore, it is desired to extract
transmission-line impedance and inductance accurately.
Most of the previous works on impedance and
inductance extraction are based on rectangular
discretization which has been shown effective for the
classical Manhattan based IC interconnect structures.
As technology advances, however, more general IC
interconnect structures, such as the X-based and
Ybased interconnect structures, have been introduced
or even already in production. Those general
interconnect structures allow wires to be routed with
non-Manhattan shapes. For the non-Manhattan
interconnect structures, rectangular discretization is
obviously not sufficient. In this project, we propose to
use the surface integral formulation with triangular
discretization to extract impedance and inductance for
the general IC transmission-line structures.
Comparative studies with the famous FASTHENRY,
FASTIMP, and IE3D show that our approach is
flexible and effective.
Subjects
inductance
surface integral
extraction
general interconnect structures
Publisher
臺北市：國立臺灣大學電子工程學研究所
Type
report
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