5 V, 8 bit, 100 MS/s fully differential CMOS sample-and-hold amplifier
Resource
Electronics Letters
Journal
Electronics Letters
Pages
-
Date Issued
1996-02
Date
1996-02
Author(s)
Chen, Chun-Chieh
DOI
0013-5194
Abstract
A 5V, 100MS/s fully differential CMOS sample-and-hold amplifier (SHA) with 8bit accuracy is proposed. Based on the stability limitations of closed-loop SHAs studied in a previous Letter (1995), the proposed SHA is implemented by an open-loop structure using the 'gain-enhanced unity-gain amplifier' to avoid the stability problem and achieve higher operation speed. Simulation results which agree well with experimental results have been obtained to demonstrate the accuracy of the proposed circuit.
Subjects
Amplifiers; CMOS integrated circuits; Sample and hold circuits
Other Subjects
Amplifiers (electronic); Aspect ratio; Computer simulation; Electric waveforms; Mathematical techniques; Multiplying circuits; Signal theory; Signal to noise ratio; Transconductance; Bias voltage; Closed loop structure; Data acquisition system; Differential mode gain; Gain enhancing factor; Microphotograph; Sample and hold circuits; CMOS integrated circuits
Type
journal article
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