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College of Electrical Engineering and Computer Science / 電機資訊學院
Electrical Engineering / 電機工程學系
0.5V SOI CMOS Dual-Threshold Circuit Technique Via DTMOS for Design Optimization of Low-Power VLSI System Applications
Details
0.5V SOI CMOS Dual-Threshold Circuit Technique Via DTMOS for Design Optimization of Low-Power VLSI System Applications
Journal
EUROSOI
Date Issued
2009-01
Author(s)
W. J. H. Lin
C. Y. Chien
J. B. Kuo
JAMES-B KUO
URI
http://scholars.lib.ntu.edu.tw/handle/123456789/351955
Type
conference paper