p-Harrow: Optical Logic Synthesis for Efficiency Optimization via Partial Harmonic Mean and Integer Partition
Journal
IEEE Journal on Emerging and Selected Topics in Circuits and Systems
Start Page
1
End Page
1
ISSN
2156-3357
2156-3365
Date Issued
2025-12-04
Author(s)
Abstract
With the advancement of high-speed and energy-efficient optical interconnect and computation, photonic integrated circuits (PICs) have become a promising alternative to traditional CMOS circuits. A PIC can be synthesized by mapping the binary decision diagram (BDD) of target functions to optical switches and combiners. However, excessive signal attenuation along the light propagation may require extra optical-electrical signal conversion, thus introducing unwanted delays. In this paper, we aim to overcome this deficiency during logic synthesis: First, we optimize the signal efficiency factor by applying the concept of harmonic mean to optimize DC combiners. Second, we properly arrange these proposed techniques in an optimal sequence of operations to form our main framework. Furthermore, we propose partial harmonic mean to minimize the hardware cost under an efficiency factor constraint. Experimental results show that our framework outperforms the state of the art in terms of efficiency factor.
Subjects
efficiency factor
harmonic mean
integer partition
logic synthesis
Photonic integrated circuit
SDGs
Publisher
Institute of Electrical and Electronics Engineers Inc.
Type
journal article