A 9Gb/s AC Coupled Chip-to-Chip Receiver

Because of technology scaling in CMOS chips, the internal clock frequency becomes faster and faster. However, the off-chip I/O signaling speed has been scaling much more slowly. To design high speed transceiver becomes an important issue.
This thesis introduces a 9Gb/s AC coupled chip to chip receiver. This receiver includes coupling capacitors, a low swing pulse receiver, and a limiting amplifier. The function of the low swing pulse receiver is to receive pulse signal from the front stage and change the pulse signal into NRZ data. The amplitude of signal from pulse receiver is still too small, so we need to amplify it. In this thesis, a modified Cherry-Hooper amplifier is used as the main amplifier. By simulation and measurement, this receiver can operate in 9Gb/s and consumes only 10.12mW, which achieves the specification of USB 3.0 (4.8Gb/s). Comparing to other works, this receiver has higher operating speed (9Gb/s) and consumes less power (10.12mW).
In conclusion, this chip is fabricated in TSMC 90nm CMOS technology. By measurement, this ac coupled receiver can be operated in 9Gb/s though 10cm FR4 microstripe line. The area of this chip is 430×255 um^2.