A dual-code-rate memoryless Viterbi decoder for wireless communication systems
Journal
IEEE International Conference on Consumer Electronics
Pages
578-579
Date Issued
2013
Author(s)
Abstract
This paper presents a novel dual-code-rate memoryless Viterbi decoder with a 4-level soft decision for wireless communication systems. Based on the proposed architecture, the survivor memory can be eliminated totally, which will significantly reduce 50% of the total power dissipation. As shown, the proposed design uses approximately 27.5 K gates in 0.18 μm CMOS technology, and its power consumption is approximately 9.8 mW at 80 MHz.
SDGs
Type
conference paper