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College of Electrical Engineering and Computer Science / 電機資訊學院
Electronics Engineering / 電子工程學研究所
Fault Modeling and Testing of Retention Flip-Flops in Low Power Designs
Details
Fault Modeling and Testing of Retention Flip-Flops in Low Power Designs
Journal
Asia and South Pacific Design Automation Conference, ASP-DAC
Date Issued
2009-01
Author(s)
CHIEN-MO LI
B. C. Bai
A. K Li
J. C.M. Li
K. C. Wu
CHIEN-MO LI
DOI
10.1109/ASPDAC.2009.4796559
URI
http://scholars.lib.ntu.edu.tw/handle/123456789/352495
SDGs
[SDGs]SDG7
Type
conference paper