Design and Implementation of a Low-Voltage Fast-Switching Mixed-Signal-Controlled Frequency Synthesizer
Resource
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: ANALOG AND DIGITAL SIGNAL PROCESSING, VOL. 48, NO. 10, OCTOBER 2001
Journal
IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing
Journal Volume
48
Journal Issue
10
Pages
961-971
Date Issued
2001-10
Date
2001-10
Author(s)
DOI
246246/200611150121858
Abstract
A new frequency synthesizer based on combining the
analog phase-locked loop (PLL) and the all digital PLL (ADPLL)
is presented. The frequency synthesizer achieves high frequency
resolution, broad frequency range, high switching speed, and low
supply voltage. The oscillator is controlled by both the digital
control word and the control voltage of the analog PLL. It is
an array oscillator implemented by symmetric load differential
inverting buffers which provide better rejection to supply noise
and fabrication variance. Fractional- divider and delay interpolation
technique are employed to enhance the divider resolution
without inducing jitter. A binary search algorithm is used to find
the proper digital frequency control word, which can be saved for
later use and greatly speed up the frequency switching process.
Fabricated using a 0.6- m SPTM CMOS process, the synthesizer
achieves a frequency range of 54–154 MHz with a frequency error
less than 1 ppm and a frequency switching time less than 10 s.
The chip consumes very little power and draws 47 mW from a
2-V supply voltage.
Subjects
Frequency synthesizer
mixed-signal control
phase-locked loop (PLL)
SDGs
Publisher
Taipei:National Taiwan University Dept Mech Engn
Type
journal article
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