A 6-bit 1.6 GS/s flash ADC in 0.18-μm CMOS with reversed-reference dummy
Journal
2006 IEEE Asian Solid-State Circuits Conference, ASSCC 2006
Pages
335-338
Date Issued
2006
Author(s)
Abstract
A 6-bit 1.6 GS/s CMOS flash ADC using reversed-reference dummy method is demonstrated in a standard 0.18-μm CMOS process. The proposed method improves linearity error at the boundary of offset averaging networks. The prototype circuit exhibits an INL of +0.32/-0.28 LSB and a DNL of +0.28/-0.28 LSB. The SNDR and SFDR achieve 32 and 44 dB at 1.6 GS/s for Nyquist input frequency. The ADC consumes 350 mW at 1.8 V supply and occupies an active chip area of 0.46 mm 2 .
SDGs
Type
conference paper