Design of a 320-MHz Continuous-Time Delta-Sigma Modulator with 5-MHz Signal Bandwidth
Date Issued
2009
Date
2009
Author(s)
Chen, Ke-Tsung
Abstract
With the advent of the third-generation (3G) era, wireless technologies on data and sounds transmission ranging from short distances to even hundreds of kilometers at its constant advances have had mobile telecommunications to be a quite important role in human life. Due to the demand for high input dynamic range, data rate, and low power, designing analog-to-digital (A/D) data converters must achieve not only the stringent conditions of higher resolution, higher bandwidth, and low power consumption, but also relax the requirements for the analog front-end parts of radio receivers. This thesis on system-level design focuses on introduction to the compensation of circuit-delayed effects and research to clock jitter; on circuit-level design it shows a better trade-off estimate on specifications through carefully analyzing, deriving out, and simulating the nonideal effects of circuit elements. The proposed implementation of the single-bit third-order low-pass continuous-time delta-sigma analog-to-digital (A/D) modulator can be mainly applied for wideband-code-division-multiple-access (i.e., so-called WCDMA) radio communications with 5-MHz signal bandwidth at sampling frequency of 320-MHz. Experimental results show that a signal-to-noise ratio (SNR) of 51.3dB (i.e., 8.2-bit ENOB) and a dynamic range of 56dB in the 2P4M 3.3-V TSMC CMOS 0.35-μm process with a R-C integrator topology. The measured current consumption is 13.6-mA.
Subjects
Analog-to-digital conversion
continuous-time
single-bit quantization
WCDMA
current-steering
oversampling
delta-sigma modulator
Type
thesis
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