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College of Electrical Engineering and Computer Science / 電機資訊學院
Electrical Engineering / 電機工程學系
Triple Threshold Static Power Minimization in High-Level Synthesis of VLSI CMOS
Details
Triple Threshold Static Power Minimization in High-Level Synthesis of VLSI CMOS
Journal
Power and Timing Modeling and Optimization Conf (PATMOS)
Date Issued
2007-09
Author(s)
H. Chen
J. B. Kuo
M. Syrzycki
JAMES-B KUO
URI
http://scholars.lib.ntu.edu.tw/handle/123456789/333622
Type
conference paper