Design and implementation of JPEG encoder IP core
Resource
Design Automation Conference, 2001. Proceedings of the ASP-DAC 2001. Asia and South Pacific
Journal
Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC
Journal Volume
2001-January
Pages
29-30
Date Issued
2001-02
Date
2001-02
Author(s)
DOI
N/A
Abstract
A complete, low cost baseline JPEG encoder soft IP and its chip implementation are presented in this paper. It features user-defined, run-time reconfigurable quantization tables, highly modularized and fully pipelined architecture. A prototype, synthesized with COMPASS cell library, has been implemented in TSMC 0.6-μm single-poly triple-metal process. It can run up to 40 MHz at 3.3 V. This IP can be easily integrated into various application systems, such as scanner, PC camera and color FAX, etc. © 2001 IEEE.
Event(s)
Asia and South Pacific Design Automation Conference 2001, ASP-DAC 2001
Subjects
Delay; Digital cameras; Discrete cosine transforms; Hardware; Image coding; Image storage; Quantization; Read-write memory; System-on-a-chip; Testing
SDGs
Other Subjects
Application specific integrated circuits; Computer aided design; Computer hardware; Cosine transforms; Digital cameras; Discrete cosine transforms; Image coding; Integrated circuit design; Optical image storage; Reconfigurable architectures; System-on-chip; Testing; Chip implementation; Delay; Design and implementations; Fully pipelined architecture; Quantization; Quantization tables; Run-time reconfigurable; System on a chip; Digital image storage
Type
conference paper
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