Manufacturing-driven Routing and Cut Mask Optimization for Advanced Technology

As process technologies continuously advance, the shrinking device dimensions and increasing device counts make chip designs much more complicated. To handle the advanced circuit designs, this dissertation considers crucial challenges in advanced technologies for circuit designs: (1) full-chip routing considering restricted design rules for one-dimensional (1D) layouts, (2) full-chip routing considering 1D directed self-assembly (DSA) via and cut templates, (3) full-chip routing considering double-post assignments and confict resolving for two-dimensional (2D) DSA process, and (4) cut mask optimization considering process variation. 1D nanowires are one of the most promising next-generation lithography technologies for 7 nm process node and beyond. The 1D nanowire process constructs a 1D nanoarray through template synthesis followed by line-end cutting with additional cut masks. To achieve better yield and manufacturability, the cut patterns shall satisfy speci ed restricted design rules, and thus it is desirable to develop a novel routing methodology to better address the challenges arising from cut patterns. In this dissertation, we propose the nanowire-aware routing system, called NWR, considering high cut-mask complexity based on a two-pass, bottom-up multilevel routing framework. Experimental results show that our nanowire-aware router can reduce cut numbers, cut spacing violations, and line-end extension length. The DSA technology for next-generation lithography has been shown its great potential for fabricating highly dense via patterns and cut masks in the sub-5 nm technology node and beyond. However, DSA via and cut optimizations were performed independently, which may induce infeasible via and cut templates and spacing violations. It is thus desirable to develop a new routing system to better address the co-optimization challenges for DSA via and cut templates. In this dissertation, we propose the simultaneous DSA via- and cut-template-aware routing system, named VCR, to practically consider both via and cut templates during routing and post-routing based on a two-pass, bottom-up multilevel routing framework. Experimental results show that VCR can reduce via- and cut-template spacing violations. 2D DSA is also an emerging lithography for the sub-5 nm process node and beyond that can substantially increase design exibility in critical routing layers and reduce the number of cuts for better yield. The state-of-the-art 2D DSA process manipulates the orientation of double posts inside guiding templates to guide block copolymers (BCPs) to form 2D patterns. However, a key challenge arises on how to correctly assign double post orientations and place cut patterns to make desired net connections for a given routing instance. In this dissertation, we propose a novel 2D DSA-compliant routing framework, named 2D-DCR, to systematically derive feasible orientation assignments for double posts to maximize routability. Specically, 2D-DCR features a complete set of new routing rules which transform the underlying physical BCP growth principles for large-scale routing, adopts a network-flow-based double-post assignment routing algorithm, and leverages a 2D DSA line-end creation property to maximally reduce line-end cuts. Experimental results show that our 2D-DCR can generate a 2D DSA-compliant routing solution with zero double post conficts, maximized routability, and minimized the number of cuts. The advanced nanometer technology imposes severe challenges on cut pattern manufacturing. A modern design may have a large number of cut patterns, and these cut patterns have small size and are usually closely positioned. The conventional OPC (Optical Proximity Correction) that minimizes the EPE (Edge Placement Error) of cut patterns at the nominal process condition alone often leads to poor process windows. To improve the cut mask printability across various process corners, process-window OPC optimizes EPE for multiple process corners, but often su ers long runtime, due to repeated lithographic simulations. This dissertation presents a general process-variation-aware mask optimization framework, namely PVOPC (Process-Variation OPC), to simultaneously minimize EPE and PV (Process-Variation) band with fast convergence. The PVOPC framework includes EPE-sensitivity-driven dynamic fragmentation, process-variation-aware EPE modeling, and correction with three new EPE-converging techniques and a systematic sub-resolution assisted feature insertion algorithm. Experimental results show that our approach achieves high-quality EPE and PV band results, which can enhance the cut pattern manufacturability.