A Low-Cost Jitter Measurement Technique for BIST Applications
Date Issued
2003
Date
2003
Author(s)
黃瑞澤
DOI
20060927122807992389
Abstract
Quality of the clock signal plays an import role in modern high-speed systems because most
activities are synchronized to the clock. However, in the existence of jitter, the clock edges may
deviate from their ideal positions. To tolerate this, one has to lengthen the clock period, which
degrades the system performance. Measuring high-speed clock jitters is a difficult task which relies on
expensive ATE (automatic test equipment) and usually requires long test time. One promising solution
to alleviate these problems is built-in self-test (BIST). Since on-chip BIST circuitry can be made close
to the signal sources under test, accessing embedded signals becomes much easier and not limited by
the bandwidth of the I/O pins.
Publisher
臺北市:國立臺灣大學電機工程學系
Type
thesis
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