strained-Si techniques and wafer bonding
Date Issued
2004
Date
2004
Author(s)
Jan, Sun-Rong
DOI
en-US
Abstract
In the past, the speed of shrinking the dimensions of the transistors can proceed with Moore’s law. However, the speed of shrinking dimensions becomes slower and slower nowadays. This is because that the dimensions shrinking will face the physical limitation. The traditional technique of shrinking dimensions is not enough. In order to continue improving the transistor speed and performance, it is essential to create new techniques.
Applying mechanical strain to transistor can enhances drive current and improves performance. In this thesis, we discuss the variation after applying strain to various semiconductors, such as NMOS, PMOS, BJT, HBT, etc… Mechanical strain can be applied to the semiconductors in the package process. Therefore, mechanical strain is also called package strain. Package strain is easy to integrate with present semiconductor techniques.
SOI（Silicon On Insulator）is one of the popular study of innovation techniques. SOI is on the base of wafer bonding. Relative to wafer bonding, we designed a multi-plane reflector applied in the RTP (Rapid Thermal Process). It can help wafer absorb energy more uniformly in RTP. We designed a device to help 4” wafer bonding.
Another popular technique is process strain. The strain can be produced in the semiconductor process. The process strain is uni-axial or local, so it is called local strain. The usual method to induce process strain is to glow a highly strained nitride cap layer beneath the NMOS. This way, there is tensile strain induced in the channel. We use some simulation software like ANSYS and ISE to simulate and discuss the effect of strain.
Subjects
應變矽技術
晶圓鍵合
wafer bonding
strained-Si techniques
Type
thesis
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