Hardware Architecture Design and Implementation of Image-Based Rendering Engine
Date Issued
2010
Date
2010
Author(s)
Chen, Chieh-Li
Abstract
Currently, the trend on the development of multimedia display system focuses on providing excellent image quality to users. As the resolution of television grows from standard definition (720×480) to quad full high definition (3840×2160), the latest iPhone 4 also provides Retina display, which has 326 dpi, already exceeds the threshold from which human eyes can tell the difference. However, the
viewing experience is restricted to high visual quality because of some limitation of current display system. Current display systems only play the data they stored
without any modification. It restrains the viewing experience of users that they can only watch multimedia contents without any interaction with them or adding their opinions into multimedia contents. Thus, we think a customized display system should be developed. The customized display system should have the ability to respond to users’ requirements and interact with users. To achieve this goal, we design an real-time interactive system, called image-based rendering engine, which introduces hardware acceleration to achieve real-time requirement and can be integrated into current display system, to bring more entertainment and to provide more interaction and more customized view experience to users.
The proposed image-based rendering engine can support several existent image-based rendering algorithms, such as 2D panorama, concentric mosaics and depth-image based rendering. The image-based rendering engine can also support a new interactive system, called Tennis Real Play, letting users to interact with the broadcast tennis video contents and play a game after they watch the Grand Slam tournaments. In order to overcome the typical hardware design challenge in accelerating rendering algorithms, such as high throughput requirement, high bandwidth requirement, programmability and low cost, we employ reconfigurable architecture and hardware sharing techniques. Besides that, we also introduce folding technique, cache mechanism and FIFO to optimize our hardware architecture.
The proposed image-based rendering engine is implementedwith TSMC 0.18μm process technology. The area of the image-based rendering engine is around 89662 gate counts with 499712 gate counts of memory. With the employ of cache mechanism, the corresponding bandwidth has reduced 82.3%. With the introduce of folding technique, the area has reduced 33.8%. And with FIFO, the total processing cycle decreases 27.4%. The proposed rendering engine can respond to users’ instruction and has rendering speed 9 times faster than CPU and 2 times faster than GPU.
Subjects
Image-based rendering
Hardware architecture
Real-time interactive system
Type
thesis
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