A 10-bit 40-MS/s Time-Domain Two-Step ADC with Short Calibration Time
Journal
IEEE Transactions on Circuits and Systems II: Express Briefs
Journal Volume
63
Journal Issue
2
Pages
126-130
Date Issued
2016
Author(s)
Chen, L.-J.
Abstract
A 10-bit 40-MS/s time-domain two-step analog-To-digital converter (ADC) in a 0.18-μm CMOS process is presented. The proposed ADC is realized without any high-gain amplifiers and its calibration time requires only 622 clock cycles, which is over 10 times less than prior digitally calibrated ADCs. The measured spurious-free dynamic range (SFDR) and signal-To-noise-plus distortion ratio (SNDR) are 61.3 dB and 53.8 dB at 40 MS/s, respectively. The power and area are 6.1 mW and 0.75 mm2, respectively. © 2004-2012 IEEE.
Subjects
calibration time; digital calibration; Time-domain; two-step ADC; voltage-To-Time converter
SDGs
Other Subjects
Calibration; Signal to noise ratio; Calibration time; Digital calibrations; Time domain; two-step ADC; Voltage-to-time converter; Analog to digital conversion
Type
journal article