Design of a Baseband Transceiver for IEEE 802.3an 10GBase-T Ethernet
Date Issued
2006
Date
2006
Author(s)
Lee, Jan-Hwa
DOI
zh-TW
Abstract
10 GBase-T was approved as IEEE standard on June 8, 2006. The IEEE 802.3an 10GBase-T project achieves the goal. In this thesis, we propose a baseband physical layer (PHY) transceiver architecture for IEEE 802.3an 10GBase-T. Algorithms for training frame synchronization, timing offset detection and compensation, automatic gain control (AGC) loop, channel equalization, and crosstalk and inteference cancellation are embedded in this receiver. A lot of non-ideal effect of receiver such as sampling phase offset, timing jitter, VCO phase noise, and fix-point quantization are analyzed and discussed. The analog circuit is the critical element of “10GBase-T high speed data transmission”. When we design the algorithm of receiver, the complexity and implementation of analog circuit are considered specifically. Besides, we propose a complete finite state machine (FSM) control flow according to the operation of every compensation loop and DSP module in this receiver to represent clearly the steps of all signal processing modules.
The goal of IEEE 802.3an 10GBase-T standard is to transmit data at 10Gbps rate on four 100m twisted pair in the long run. We are mainly aimed at “CAT6-55m channel” to present the evaluation and design, and will achieve 10Gbps transmission under 100m copper wire in the future.
Subjects
百億位元
乙太網路
百億位元乙太網路
10GBase-T
Ethernet
10G Ethernet
Type
thesis