Formal-Assisted Multi-Corner Multi-Mode Timing Analysis and Optimization Techniques
Date Issued
2012
Date
2012
Author(s)
Tsai, Shih-Heng
Abstract
Timing closure has always been the biggest bottleneck in the modern VLSI design flow. To assure the correctness of circuit timing behavior, both rigorous timing analysis and powerful timing optimization are required.
Traditional timing analysis techniques include static timing analysis (STA) and dynamic timing analysis (DTA). STA can be considered as a delay upper bound propagation process which simply takes the maximum delay at every circuit node, while DTA requires the input signal information (pattern) and simulate the circuit timing behaviors in a given time period with much larger run time. In the past decades, traditional STA has been a fast and decent tool to compute delay upper bound by ignoring signal interactions such as false paths and multiple input transitions. However, to achieve higher accuracy which is needed in modern design scale, such interactions must be taken into consideration.
In addition, recent challenges on timing verification come from the unpredictability due to process variations (multiple corners) and the demand for low power design methodologies (multiple power modes with multiple supply voltages and operating frequencies). These multiple design scenarios, so called multi-corner multi-mode (MCMM), have significantly increased the complexities of both timing analysis and optimization. Traditional timing analysis techniques usually handle one or two scenarios at a time and require a great amount of iterations and run time to complete full circuit MCMM timing analysis. Moreover, traditional timing optimization approaches, such as dynamic-programming-based buffer insertion techniques, are unable to handle MCMM simultaneously. As a result, we need to either iteratively optimize the design one mode/corner at a time, leading to the timing convergence problem, or take a conservative approach in defining the timing constraints that ends up unsatisfiable for the original design specification. In short, MCMM timing constraints would attenuate the design margin and greatly reduce the yield.
In this dissertation, we propose an integrated formal-assisted timing analysis and optimization flow which solves the MCMM issues and increases the capability of the timing verification techniques. The overall verification flow includes three parts: First, a unified Multi-Corner Multi-Mode Static Timing Analyzer (MCMM-STA) is proposed to efficiently compute the worst-case delay among various process corners; Second, a Formal-Assisted Timing Analysis (FATA) technique is applied to formally detect false paths identified by our MCMM-STA engine, consider multiple-input transitioning effects in delay calculations, and generate input transition patterns for true critical paths in timing debugging and post-layout simulations; And third, a novel Semi-Formal Buffer Insertion (SFBR) algorithm is devised to compute a minimum-cost buffer placement for the MCMM timing constraints based on the results of our MCMM-STA and FATA.
Subjects
Timing Analysis
Timing Optimization
Formal Methods
Multi-corner Multi-mode
Type
thesis
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