Parallel embedded block coding architecture for JPEG 2000
Resource
IEEE Transactions on Circuits and Systems for Video Technology 15 (9): 1086-1097
Journal
IEEE Transactions on Circuits and Systems for Video Technology
Journal Volume
15
Journal Issue
9
Pages
1086-1097
Date Issued
2005
Date
2005
Author(s)
Abstract
This paper presents a parallel architecture for the Embedded Block Coding (EBC) in JPEG 2000. The architecture is based on the proposed word-level EBC algorithm. By processing all the bit planes in parallel, the state variable memories for the context formation (CF) can be completely eliminated. The length of the FIFO (first-in first-out) between the CF and the arithmetic encoder (AE) is optimized by a reconfigurable FIFO architecture. To reduce the hardware cost of the parallel architecture, we proposed a folded AE architecture. The parallel EBC architecture can losslessly process 54 MSamples/s at 81 MHz, which can support HDTV 720p resolution at 30 frames/s. © 2005 IEEE.
Subjects
Discrete wavelet transform (DWT); Ebc with optimized truncation (EBCOT); Embedded block coding (EBC); Image processing; JPEG 2000; Parallel processing
Other Subjects
Discrete wavelet transforms (DWT); Ebc with optimized truncation (EBCOT); Embedded block coding (EBC); JPEG 2000; Parallel processing; Computer architecture; Computer science; Embedded systems; Encoding (symbols); Information technology; Optimization; Parallel processing systems; Wavelet transforms; Block codes
Type
journal article
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