Optimal design of megabyte second-level caches for minimizing bus traffic in shared-memory shared-bus multiprocessors
Resource
System Sciences, 1992. Proceedings of the Twenty-Fifth Hawaii International Conference on
Journal
Twenty-Fifth Hawaii International Conference on System Sciences
Pages
-
Date Issued
1992-01
Date
1992-01
Author(s)
Wu, Le-Chun
DOI
N/A
Abstract
As the design of shared-memory shared-bus multi-processors is heading toward employing megabyte second-level caches, how to optimize the design of the second-level caches in order to minimize the traffic on the shared bus and thus improve the system scalability is of great interest. The paper presents a comprehensive study on this issue through extensive trace-driven simulations and concludes with a few general and effective rules.>
Type
journal article
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