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College of Electrical Engineering and Computer Science / 電機資訊學院
Electronics Engineering / 電子工程學研究所
Optimal spacing and capacitance padding for general clock structures
Details
Optimal spacing and capacitance padding for general clock structures
Journal
Asian and South Pacific Design Automation Conference (ASP-DAC)
Date Issued
2001-01
Author(s)
Yu-Min Lee
Hing Yin Lai
CHUNG-PING CHEN
DOI
10.1145/370155.370297
URI
http://scholars.lib.ntu.edu.tw/handle/123456789/294594
SDGs
[SDGs]SDG9
Type
conference paper