High-throughput dual-mode single/double binary map processor design for wireless wan
Journal
IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation
Pages
83-87
Date Issued
2008
Author(s)
Abstract
In this paper we present the VLSI implementation of a high-throughput enhanced Max-log-MAP processor that supports both single-binary (SB) and double-binary (DB) convolutional turbo codes. The combined hybrid-window (HW) and parallel-window (PW) MAP decoding is introduced to support arbitrary frame sizes with high throughput. A 1.28 mm 2 dual-mode (SB/DB) 2PW-1HW MAP processor is also implemented in TSMC 0.13 mum CMOS process to verify the proposed approaches. The proposed MAP processor can be used as hardware accelerators in multistandard platform for wireless WAN with low cost and low energy.
SDGs
Type
conference paper