Skip to main content
English
中文
Log In
Log in
Log in with ORCID
NTU Single Sign On
Have you forgotten your password?
Home
College of Electrical Engineering and Computer Science / 電機資訊學院
Computer Science and Information Engineering / 資訊工程學系
SCALABLE HIGH HARDWARE UTILIZATION EFFICIENCY LDPC DECODER
Details
SCALABLE HIGH HARDWARE UTILIZATION EFFICIENCY LDPC DECODER
Resource
16th VLSI Design/CAD symposium
Journal
16th
Journal Volume
VLSI
Pages
-
Date Issued
2005
Date
2005
Author(s)
Chien, Yi-Hsing
Ku, Mong-Kai
URI
http://ntur.lib.ntu.edu.tw//handle/246246/232450
Type
conference paper
