A Parallel Test Pattern Generation Algorithm to Meet Multiple Quality Objectives
Journal
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Journal Volume
30
Journal Issue
11
Pages
1767-1772
Date Issued
2011-11
Author(s)
Abstract
This paper proposes a bit-level parallel ATPG algorithm (SWK) that generates multiple test patterns at a time. This algorithm converts decisions into bitwise logic operation so that W (CPU word size) test patterns are searched independently. Multiple objectives for different quality metrics can therefore be achieved in a single test generation process. Experimental results on ISCAS'89 and IWLS'05 benchmark circuits show that SWK test sets are better in many quality metrics than traditional 50-detect test sets, while the length of the former is shorter. Also, patterns selected from large N-detect pattern pool cannot achieve the same or higher quality than patterns generated by SWK.
Type
journal article