Steady-State Analysis of Pulse-Skipping PFC-Control Schemes for AC/DC Power Converters
Date Issued
2012
Date
2012
Author(s)
Hung, Yu
Abstract
Power factor correction (PFC) is a must nowadays for many power supply applications in which the power is derived directly from a power line. For many years, a boost converter cascaded by a flyback converter has been a popular circuit configuration for many applications. Two feedback control loops are usually used; one controlling the input power factor and providing rough bulk capacitor voltage regulation, and the other one controlling the flyback converter to provide a tightly regulated output voltage. This approach uses two power stages and two separate controller integrated circuits (ICs).
There has been a trend to simplify the circuit configuration and to reduce the overall cost by developing the so-called single-stage PFC in which one power stage and one controller IC are used. However, there are disadvantages associated with such approach. One of those is higher power switch losses. And the other is that additional power stage component is usually needed to prevent the bulk voltage from going too high.
Recently, there has been a trend to cut down the overall cost even at the expense of power factor, or more precisely, the input harmonic current, as long as it meet minimum
requirement. There was a strategy reported, the so-called pulse-skipping PFC converter to achieve the goal mentioned above. In this strategy, there still are two power stages
used but there is only one feedback control IC to provide gate drive signals to the main switches of the two stages. The front-stage boost converter is always operated in
discontinuous conduction mode to achieve acceptable power factor. The second dc/dc stage is the flyback converter. The gate drive signal to the flyback converter is the same as the conventional strategy, but the gate drive signal to the boost converter is used with skipping the pulses. This strategy may keep the input harmonic current in acceptable range and still manage the bulk voltage to stay within reasonable range.
The focus of the present thesis is to investigate such a strategy which was patented but not fully studied and certainly not yet implemented. Mathematical analysis are
conducted to reveal the complicated relationships, particularly the intermediate bulk voltage dependency on circuit component values, working conditions, and the
pulse-skipping strategy. Simulations run are performed to verify the mathematical results. The conclusions from this effort indicate that there is an advantage but also serious drawbacks of such an approach.
Subjects
power factor correction
two-stage PFC converter
single-loop control
DCM boost PFC
pulse skipping mode
low power application
Type
thesis
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