Design and Implementation of 30 GHz Phase-Locked Loop in a 0.18-μm CMOS Technology
Date Issued
2011
Date
2011
Author(s)
Peng, Ciao-Ling
Abstract
With the advances of the silicon integrated circuit technologies, radio-frequency IC designs are motivated toward higher frequency. Due to the rapid evolution of the wireless communication in industrial, scientific and medical band, the demands for the low-cost and low-power integrated circuit have been increased. To ensure millimeter-wave circuits and systems work properly, the fabrication technology must be scaled down for high-frequency operations. Unfortunately, there exists a tradeoff between cost and circuit performance. However, it is still a challenging task for the designer to implement millimeter-wave circuits while sustaining lower cost efficiently.
In this thesis, to reduce the cost of the fabricated circuit, a technique of the circuit topology is adopted such that a 30.4 GHz PLL can be realized in standard CMOS technologies. First, independent PD and FD are employed while the conventional PFD structure limits the operating frequency apparently. In addition, the synthetic quasi-TEM transmission line is introduced to the VCO for the small area and higher operating frequency, facilitating circuit implementation in standard 0.18-μm CMOS technologies. Meanwhile, by using the well-designed transmission line, the VCO can be more stable due to good shielding capability. With a standard design procedure of PLL, the experimental results are presented completely for demonstrations. Operated at a 1.8-V supply voltage, the fabricated circuit consumes a dc power of 64.8mW.
Subjects
phase-locked loop
synthetic quasi-TEM transmission line
millimeter-wave
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