A Low-Power Digital Matched Filter for Direct-Sequence Spread Spectrum Signal Acquisition
Journal
IEEE Journal of Solid-State Circuits
Journal Volume
36
Journal Issue
6
Pages
933-943
Date Issued
2001-06
Author(s)
M. L. Liou
Abstract
This paper presents a low-power 128-tap dual-channel direct-sequence spread-spectrum (DSSS) digital matched-filter chip. Design techniques used to reduce the power consumption of the system include latch-based register file filter structure, a high-rate compression scheme, optimized compressor cells, and semicustom layout design. To further reduce the power consumption and the hardware requirement of the clock tree, a double-edge-triggered clocking scheme is adopted. The proposed chip is fabricated using a 0.8-μm standard CMOS process. As the experimental results of the chip indicate, the matched filter can operate at 50 MHz and dissipates 184 mW at 5-V supply voltage. The supply voltage can be scaled down to 2 V for lower speed applications. As a consequence, the proposed design has low power consumption and can be used for code acquisition of DSSS signals in portable systems.
Subjects
Digital matched filter; Double edge trigger; Gated pullup; High rate compressor; Prefiltering structure; Spread spectrum
SDGs
Other Subjects
Code acquisition; Digital matched filter; Double edge trigger; CMOS integrated circuits; Direct sequence systems; Electric power supplies to apparatus; Integrated circuit layout; Signal detection; Digital filters
Type
journal article