Publication: A 0.9V 15fJ/conversion-step 8-bit 1.5GS/s two-step SAR ADC
| cris.lastimport.scopus | 2025-05-07T21:57:52Z | |
| cris.virtual.department | Electrical Engineering | en_US |
| cris.virtual.department | Electronics Engineering | en_US |
| cris.virtual.orcid | 0000-0002-7666-4984 | en_US |
| cris.virtualsource.department | 63448d80-1445-4b85-b7f6-62de8e5cf19e | |
| cris.virtualsource.department | 63448d80-1445-4b85-b7f6-62de8e5cf19e | |
| cris.virtualsource.orcid | 63448d80-1445-4b85-b7f6-62de8e5cf19e | |
| dc.contributor.author | Hu, Y.-S. | en_US |
| dc.contributor.author | Huang, P.-C. | en_US |
| dc.contributor.author | Yang, M.-T. | en_US |
| dc.contributor.author | Wu, S.-W. | en_US |
| dc.contributor.author | HSIN-SHU CHEN | en_US |
| dc.date.accessioned | 2020-06-11T06:48:28Z | |
| dc.date.available | 2020-06-11T06:48:28Z | |
| dc.date.issued | 2017 | |
| dc.description.abstract | An 8-bit 1.5GS/s 2-way two-step SAR ADC operating at 0.9V is presented in this paper. A low-skew demultiplexer circuit is proposed to synchronize the sampled signals of the two sub-ADCs with the edge of global clock. The sharing of the quarter clock phase generator leads to lower power consumption. A charge-sharing technique without any interstage residue amplifier not only makes the two-step SAR sub-ADC low-power, but also accelerates its conversion rate. A self-trigger latch (STL) technique is also used to reduce digital power consumption. The prototype ADC in 40nm CMOS consumes 3.1mW at 1.5GS/s with a 0.9V supply. It achieves a Nyquist SNDR of 44.5dB and results in an FoM of 15fJ/c.-s. © 2016 IEEE. | |
| dc.identifier.doi | 10.1109/ASSCC.2016.7844140 | |
| dc.identifier.scopus | 2-s2.0-85015160836 | |
| dc.identifier.uri | https://scholars.lib.ntu.edu.tw/handle/123456789/501233 | |
| dc.identifier.url | https://www.scopus.com/inward/record.uri?eid=2-s2.0-85015160836&doi=10.1109%2fASSCC.2016.7844140&partnerID=40&md5=02dfffe1bb45b40ca77a99e8ef999ca9 | |
| dc.relation.ispartof | 2016 IEEE Asian Solid-State Circuits Conference, A-SSCC 2016 - Proceedings | |
| dc.relation.pages | 81-84 | |
| dc.subject | Analog-to-digital converter (ADC); charge sharing; energy-efficient; low-skew demultiplexer; self-triggered latch; successive-approximation register (SAR); two-step | |
| dc.subject.classification | [SDGs]SDG7 | |
| dc.subject.other | Clocks; Demultiplexing; Electric power utilization; Energy efficiency; Analog to digital converters; Charge sharing; Demultiplexers; Energy efficient; self-triggered latch; Successive approximation register; two-step; Analog to digital conversion | |
| dc.title | A 0.9V 15fJ/conversion-step 8-bit 1.5GS/s two-step SAR ADC | en_US |
| dc.type | conference paper | |
| dspace.entity.type | Publication |