A 3.1-10.6 GHz CMOS cascaded two-stage distributed amplifier for ultra-wideband application
Resource
Advanced System Integrated Circuits 2004. Proceedings of 2004 IEEE Asia-Pacific Conference on
Journal
Advanced System Integrated Circuits 2004
Pages
Proceeding-s
Date Issued
2004-08
Date
2004-08
Author(s)
Chen, Kuan-Hung
Wang, Chorng-Kuang
DOI
N/A
Abstract
In this paper, a CMOS cascaded two-stage distributed amplifier for ultra-wideband (UWB) application is presented. The circuit using two-stage cascaded topology achieves better gain-bandwidth product performance than conventional CMOS distributed amplifiers. The simulated gain is 18dB with /spl plusmn/1dB gain flatness over 3.1/spl sim/10.6 GHz bands. Input and output are matched to 50/spl Omega/, and the return losses of input and output are below -10dB and -9dB respectively. The power dissipation is 54mW with 1.8V power supply. The circuit was fabricated in 0.18-/spl mu/m 1P6M RF CMOS process.
SDGs
Type
journal article
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