A 10-Bit Binary-Weighted DAC with Digital Background LMS Calibration
Journal
IEEE Asian Solid-State Circuit Conference
Pages
352-355
Date Issued
2007-11
Author(s)
Abstract
A 10-bit binary-weighted DAC utilizes identical reduced a gap fail of gray voltage levels and enhanced IC yield. transistors with different overdrive voltages to achieve small area and high speed. Employing LMS calibration, the proposed current-steering DAC can be digitally calibrated in the background. The measured SFDR of the output signal at 61 kHz can be improved by 19 dB at 1 GS/s. The 10-bit DAC occupies 0.2 mm 2 in a 0.18-µm CMOS technology and consumes 27 mW from a 1.8-V supply.
SDGs
Type
conference paper