Low voltage CMOS four-quadrant multiplier
Resource
Electronics Letters
Journal
Electronics Letters
Journal Volume
30
Journal Issue
25
Pages
2125-2126
Date Issued
1994-12
Date
1994-12
Author(s)
Abstract
A new low voltage CMOS four-quadrant multiplier is presented. Simulation results show that, for a power supply of ±1.5V the differential linear range is over ±0.8V with the linearity error less than 2%. The total harmonic distortion is less than 1% with the input range up to ±0.6V, The simulated -3dB bandwidth of this multiplier is about 12MHz. The proposed circuit is expected to be useful in low-voltage analogue signal processing applications. © 1994, IEE. All rights reserved.
Subjects
CMOS integrated circuits; Multiplying circuits
Other Subjects
Buffer circuits; CMOS integrated circuits; Computer simulation; Electric current control; Frequency stability; Gain control; Harmonic analysis; Integrated circuit layout; Transistors; Triodes; VLSI circuits; Voltage control; Four quadrant multiplier; Harmonic distortion; Software package SPICE; Multiplying circuits
Type
journal article
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