Low-latency Voltage-Racing Winner-Take-All (VR-WTA) circuit for acceleration of learning engine
Journal
2017 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2017
Date Issued
2017
Author(s)
Abstract
Neural networks are widely used in various fields due to their superior learning ability. Concurrent with the increase in their popularity, the rise of Big Data has resulted in increased computational requirements and processing power. To meet the requirements of real-time learning and classification, the process of finding the maximum value proves to be the performance bottleneck, and therefore needs to be accelerated. To the best of our knowledge, most studies reported in the literature cannot satisfy the requirements of low latency, high resolution, and low power consumption simultaneously. In this paper, we propose a Voltage-Racing Winner-Take-All (VR-WTA) circuit for acceleration of real-time learning engine. The linear delay elements transform multiple bits into different current racing speeds, and the fastest winner is detected by a sense-amplifying detector. The resolutions are scalable and reconfigurable for the needs of different applications. Simulation results show that the proposed VR-WTA achieves more than three times latency reduction, and saves 81% of the unnecessary power consumption compared with related works. Moreover, these results are also evaluated under 100 rounds of Monte Carlo simulations with different corner conditions and process/voltage/temperature (PVT) variations to guarantee that our approach works properly.
SDGs
Type
conference paper