Low-latency Voltage-Racing Winner-Take-All (VR-WTA) circuit for acceleration of learning engine

Journal

2017 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2017

Date Issued

2017

Author(s)

Wu, C.-H.

Chen, T.-S.

Lee, D.-Y.

Liu, T.-T.

Wu, A.-Y.

DOI

10.1109/VLSI-DAT.2017.7939641

URI

https://scholars.lib.ntu.edu.tw/handle/123456789/499795

URL

https://www.scopus.com/inward/record.uri?eid=2-s2.0-85021411330&doi=10.1109%2fVLSI-DAT.2017.7939641&partnerID=40&md5=c276d0ae3c69f6a70c279b0dfb61f2e4

SDGs

[SDGs]SDG7

Type

conference paper