H.264移動估測器之設計與製作
Design and Implementation of an H.264 Motion Estimator
Date Issued
2005
Date
2005
Author(s)
Jheng, He-Cih
DOI
en-US
Abstract
H.264/AVC [1][2] is the latest international video coding standard developed by the ITU-T Video Coding Experts Group and the ISO/IEC Moving Picture Experts Group. It can achieve higher coding efficiency than these previous standards such as MPEG-4 and H.263. With the advent of new video standards such as MPEG-4 part-10 and H.264/H.26L, demands for advanced video coding (AVC), particularly in the area of variable block searching motion estimation (VBSME), are increasing. However, AVC requires a much higher computational complexity due to the use of variable block-size motion estimation and mode decision. This has led to research into suitable flexible hardware architectures to perform the various types of VBSME.
In this Thesis, we design and implement a 1-D VLSI architecture for full-search variable block size motion estimation (FSVBSME). The variable block size, sum of absolute differences (SAD) computation is performed by reusing the results of smaller sub-block computations. These are permuted and combined by incorporating a shuffling mechanism within each processing element (PE). Whereas a conventional 1-D architecture can process only one motion vector, this architecture can process up to 41 sub-blocks of motion vectors (MV) (within a macroblock) in a comparable number, 256 clock cycles.
Although some relevant algorithms for motion estimation have been developed, we decide to implement a full search algorithm for block matching-based motion estimation due to its regularity and precision. The full search algorithm is suitable for hardware-oriented architecture and implementation.
To achieve high efficiency or real-time application, it is important to use parallel processing elements (PE) in a motion estimation architecture. Besides, the trade-off between low-power constraint and small-area requirement is also a challenge. As a result, we adopt a 1-D array BSME architecture to implement our motion estimator.
The final performance of this chip is 200MHz with a power consumption of 302 mW under 1.8V power supply, and the frames that this chip can process are 123 fps with the CIF size (352x288). This prototype chip of H.264/MPEG-4 AVC Motion Estimation System is realized in TSMC 0.18μm 1P6M technology and using Artisan 0.18μm standard CMOS cell library via CIC. And this chip also includes test consideration. The total gate count is about 202 K and die size is 2.3x2.3 including two on-chip memories.
Subjects
h.264
Type
thesis
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