Verification and Implementation of Bus Functional Models for USB System
Date Issued
2009
Date
2009
Author(s)
Wang, Hung-Po
Abstract
Due to the increasing complexity of modern SoC designs, verification has become one of the bottlenecks of the entire IC design process [5]. Current verification strategy, based on traditional hardware simulation, is not able to fulfill designer’s need efficiently because of the escalation simulation time. Functional correctness is the most fundamental requirement for all hardware design. How to reduce the simulation time and increase the functional coverage are the primary issues that designers and researchers need to solve right away. In this thesis I provide a set of Universal Serial Bus (USB) Bus Functional Models (BFM), congruent to USB specification. By testing design under verification (DUV) in the behavior level, simulation time can be reduced. The BFM are configurable and programmable. We could construct all topologies of the USB system using the BFM. USB BFM can become a golden model, send packets to DUV, and receive packets from DUV to check if it’s functional correctly. Finally we will provide a USB simulation environment using USB BFM for designers to be a reference in chip or ip design
Subjects
Bus Functional Model
Type
thesis
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