VLSI Design of Convolutional/Turbo Decoder Based on Triple-Mode VA/MAP Kernel for 3rd GPP System
Date Issued
2004
Date
2004
Author(s)
Shen, Pei-Ling
DOI
en-US
Abstract
The needs of 3rd generation mobile communication system (3G) and its multi-media services are growing in the near feature. One of key element in 3G is channel coding. Channel coding minimizes the effects of noise and interference on the transmitted signal at the physical layer. According to the 3rd Generation Partnership Project (3GPP) technical specification two channel coding scheme, turbo code and convolutional code, are applied. Both of these channel coding schemes are typically computationally intensive and power-consuming tasks and is therefore normally implemented in a dedicated hardware block.
In 3G system, the voice and data streams use convolutional and turbo code schemes, respectively. Typically, the corresponding convolutional and turbo code decoder are built separately. In the state of art, dual-mode designs combine hardware of those two decoder. However, there is no combination timing of two algorithms.
The objective of this thesis is based on a methodology of associate timing and hardware in two decoding algorithms, then implement an FEC kernel which complaint with 3Gpp standard. After exploiting the fact that both convolutional and turbo decoders are based on similar trellis decoders, we built both decoding operations in one single architecture to achieve hardware association; besides, we propose a triple-mode (convolutional decoding, turbo decoding and convolutional decoding while turbo decoding) timing charts by complementing idle time of each other. This results in a reduced cost solution through resource sharing. Finally, we implemented this design in Artisan 0.18 cell-library. This FEC kernel run at clock rate equals 100MHz, and decodes a 4.18Mbps turbo encoded data stream with 6 iterations.
Subjects
維特比演算法
渦輪碼
Turbo Code
Viterbi Algorithm
Type
thesis
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