A delay-locked loop with statistical background calibration
Journal
IEEE Transactions on Circuits and Systems II: Express Briefs
Journal Volume
55
Journal Issue
10
Pages
961-965
Date Issued
2008-10
Author(s)
Shao-Ku Kao
Abstract
A delay-locked loop (DLL) using a statistical background calibration circuit (SBCC) is presented. This SBCC is utilized to calibrate the charge pump. Eighty identical arbiters with random mismatch effectively measure the phase error between the input and output clocks. Therefore, the static phase error of the DLL is improved. The proposed DLL has been fabricated in 0.18-μm CMOS process. Its active area is 0.078 mm2. The power dissipation is 35 mW for the supply of 1.8 V and the input clock of 1.2 GHz. This DLL operates from 900 MHz to 1.2 GHz. The measured static phase error is 15.45 and 2.92 ps without and with the SBCC, respectively at 1.2 GHz. © 2008 IEEE.
Subjects
Calibration; Charge pump circuits; Clocks; Errors; Active area; Background calibrations; Charge pump; CMOS processs; Delay-locked loops; Input and outputs; Phase error; Static phase errors; Delay lock loops
SDGs
Other Subjects
Calibration; Charge pump circuits; Clocks; Errors; Active area; Background calibrations; Charge pump; CMOS processs; Delay-locked loops; Input and outputs; Phase error; Static phase errors; Delay lock loops
Type
journal article