Self-Testing and Self-Calibration Technique for Digital to Analog Converter
Date Issued
2006
Date
2006
Author(s)
Ma, Yuan-Lang
DOI
en-US
Abstract
The digital to analog converter (DAC) is a key component in signal processing and telecommunication applications. One major design challenge is to achieve high static and dynamic linearity in the existence of inevitable process variations, e.g., the systematic Vth gradient across the wafer or the random device mismatch.
Various layout techniques have been developed to enhance the achievable resolution by canceling out the process variation gradient. However, both the required large current source array and the complex routing introduce parasitic capacitance that poses negative impact on the dynamic performance. Furthermore, the final resolution is not predictable during the design phase and could just try-and-error to tune-up the resolution to meet the specification.
Calibration techniques that intend to enhance the DAC resolution have been reported. Some works require an extra built-in high resolution converter (DAC or ADC) as the embedded tester and thus may not be suitable for some applications.
Trimming technique use an operation amplifier (OpAmp) and a reference current source used to continuously charge a capacitor that stores the bias voltage of each current source in background. However, the differences between the OpAmp offset voltages may result in large current mismatch. Fuse array is utilized to adjust the DAC INL during the final test. While guaranteeing the final resolution, it requires large area overhead for the fuse array and an accurate external tester, which raises the test cost.
The proposed DAC self-testing and self-calibration technique aims at reducing the induced area overhead and the required design efforts. In our technique, the lower significant bits are duplicated. Together with an analog comparator, this duplicated sub-DAC supports both self-testing and self-calibration. A prototype 14-bit DAC has been designed and fabricated in TSMC 0.35 µm technology. The results show that the proposed technique is able to greatly improve the DAC’s static and dynamic performance with low area overhead and shortened design routine.
Subjects
自我測試
自我校正
數位類比轉換器
self-testing
self-calibration
dac
Type
thesis
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