NAND型快閃記憶體上之NOR型快閃記憶體的模擬策略
A NOR Emulation Strategy over NAND Flash Memory
Date Issued
2007
Date
2007
Author(s)
Lin, Chien-Hung
DOI
en-US
Abstract
This work is motivated by a strong market demand in the replacement of NOR flash memory with NAND flash memory to cut down the cost in many embedded-system designs, such as mobile phones. Different from LRU-related caching or buffering studies, we are interested in prediction-based prefetching based on given execution traces of applications. An implementation strategy is proposed in the storage of the prefetching information with limited SRAM and run-time overheads. An efficient prediction procedure is presented based on information extracted from application executions to reduce the performance gap between NAND flash memory and NOR flash memory in reads. With the behavior of a target application extracted from a
set of collected traces, we show that data access over NOR flash memory is responded effectively over SRAM that serves as a cache for NAND flash memory.
Subjects
NAND型
NOR型
快閃記憶體
資料快取
NAND
NOR
flash memory
data caching
Type
thesis